Power optimization methodology for multimedia applications implementation on reconfigurable platforms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2799, Issue , 2003, Pages 430-439

  Tatas, K ^a   Siozios, K ^a   Soudris, D ^a   Masselos, K ^b   Potamianos, K ^b   Blionas, S ^b   Thanailakis, A ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

^b Intracom Holdings SA   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

ALGORITHMIC TRANSFORMATION; MEMORY HIERARCHY; MULTIMEDIA APPLICATIONS; POWER EFFICIENCY; POWER EFFICIENT; POWER OPTIMIZATION; RECONFIGURABLE PLAT-FORMS; REGISTER TRANSFER LEVEL;

RECONFIGURABLE HARDWARE;

EID: 33750415922     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39762-5_49     Document Type: Article

References (9)

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