Multiplier less FFT processor architecture for signal and image processing

Proceedings - 2005 International Conference on Intelligent Sensing and Information Processing, ICISIP'05

Volumn 2005, Issue , 2005, Pages 326-330

  Prasanthi, R ^a   Anuradha, V ^a   Sahoo, S K ^a   Shekhar, Chandra ^b  

^a BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

^b CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

FFT PROCESSORS; MULTIPLIERS; POWER CONSUMPTION;

ADDERS; ALGORITHMS; FAST FOURIER TRANSFORMS; IMAGE PROCESSING; PROBABILITY DENSITY FUNCTION; VLSI CIRCUITS;

COMPUTER ARCHITECTURE;

EID: 33750144707     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICISIP.2005.1529470     Document Type: Conference Paper

References (5)

1. Willim T. Cochran.James W. Coolet, "What is the fast Fourier Transform?". IEEE Transactions On Audio and Electro acoustics, Vol. AU-15, No.2. pp. 45-55, June 1967
2. P. Song And G.De Micheli, " Circuit And Architecture Tread Off For High Speed Multiplication" IEEE J. of Solid State Circuits, Vol.2, No.9, November 1997.
3. Hesham Abdulaziz Al-Twaijry, " Area And Performance Optimized CMOS Multipliers", Ph.D Thesis.
4. Kaushik Maharantna, Eckhard Grass And Ulrich Jagdhold, "A 64-point Fourier Transform chip For High Speed Wireless LAN Application Using OFDM", IEEE J. of Solid State Circuits, Vol.39, No.3, pp. 484-493, March 2004.
5. John L Hennesy & David A, Patterson " Computer Architecture A Quantitative Approach" Second edition; A Harcourt Publishers International Company