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Volumn 2006, Issue , 2006, Pages 302-305
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Reconstituted wafer technology for heterogeneous integration
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Author keywords
[No Author keywords available]
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Indexed keywords
BATCH PROCESSING;
CARRIER WAFERS;
SUB-MICRON ACCURACY;
THERMAL BUDGET;
CHIP SCALE PACKAGES;
SEDIMENTATION;
SILICON WAFERS;
SUBSTRATES;
INTEGRATED CIRCUITS;
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EID: 33750139339
PISSN: 10846999
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (6)
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References (7)
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