Translating between itanium and sparc memory consistency models

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Volumn 2006, Issue , 2006, Pages 170-179

  Higham, Lisa ^a   Jackson, LillAnne ^a  

^a UNIVERSITY OF CALGARY   (Canada)

Author keywords

Itanium; Memory consistency models; Multi processors; Program transformations; Sparc

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; PROBLEM SOLVING; SEMANTICS;

BARRIER INSTRUCTIONS; MULTIPROCESSOR ARCHITECTURE; PORT PROGRAMS; SPARC ARCHITECTURE;

STORAGE ALLOCATION (COMPUTER);

EID: 33749573941     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1148109.1148138     Document Type: Conference Paper

References (16)

1. S. V. Adve and M. D. Hill. Weak ordering - a new definition. In Proc. 17th Int'l Symp. on Computer Architecture, pages 2-14, May 1990.
2. M. Ahamad, R. Bazzi, R. John, P. Kohli, and G. Neiger. The power of processor consistency. In Proc. 5th Int'l Symp. on Parallel Algorithms and Architectures, pages 251-260, June 1993. Technical Report GIT-CC-92/34, College of Computing, Georgia Institute of Technology.
3. M. Ahamad, G. Neiger, J. E. Burns, P. Kohli, and P. W. Hutto. Causal memory: Definitions, implementations, and programming. Distributed Computing, 9:37-49, 1995.
4. P. Chatterjee and G. Gopalakrishnan. Towards a formal model of shared memory consistency for Intel itaniumtm. In Proc. 2001 IEEE International Conference on Computer Design (ICCD), pages 515-518, Sept 2001.
5. K. Gharachorloo. Memory Consistency Models for Shared-Memory Multiprocessors. PhD dissertation, Department of Electrical Engineering, Stanford University, 1995.
6. J. Goodman. Cache consistency and sequential consistency. Technical Report 61, IEEE Scalable Coherent Interface Working Group, March 1989.
7. L. Higham and L. Jackson. Translating between itanium and spare memory consistency models. Technical report, Department of Computer Science, The University of Calgary, May 2006.
8. L. Higham, L. Jackson, and J. Kawash. Specifying memory consistency of write buffer multiprocessors. ACM Trans. on Computer Systems. To appear.
9. L. Higham, L. Jackson, and J. Kawash. Capturing register and control dependence in memory consistency models with applications to the Itanium architecture, May 2006. Submitted to: DISC 2006.
10. L. Higham, J. Kawash, and N. Verwaal. Defining and comparing memory consistency models. In Proc. 10th Int'l Conf. on Parallel and Distributed Computing Systems, pages 349-356, October 1997.
11. Intel Corporation. A formal specification of the intel itanium processor family memory ordering, http://www.intel.com/, Oct 2002.
12. V. Iosevich and A. Schuster. A comparison of sequential consistency with home-based lazy release consistency for software distributed shared memory. In International Conference on Supercomputing, pages 306-315, September 2004.
13. L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. on Computers, C-28(9):690-691, September 1979.
14. R. J. Lipton and J. S. Sandberg. PRAM: A scalable shared memory. Technical Report 180-88, Department of Computer Science, Princeton University, September 1988.
15. D. L. Weaver and T. Germond, editors. The SPARC Architecture Manual version 9. Prentice-Hall, 1994.
16. Y. Yang, G. Gopalakrishnan, G. Lindstrom, and K. Slind. Analyzing the intel itanium memory ordering rules using logic programming and sat. Technical Report UUCS-03-010, University of Utah, 2003.