Towards a formal model of shared memory consistency for Intel Itanium™

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 515-518

  Chatterjee, P ^a   Gopalakrishnan, G ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER PROGRAM LISTINGS; DATA STRUCTURES; DIGITAL LIBRARIES; FORMAL LOGIC; MATHEMATICAL MODELS; PROGRAM PROCESSORS; SEMANTICS;

SHARED MEMORY SYSTEMS;

DATA STORAGE EQUIPMENT;

EID: 0035181646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Coherence and MP ordering
2. Causal memory: Definitions, implementation and programming
3. Shared memory consistency models: A tutorial
4. Sequential consistency and the lazy caching algorithm