Massively parallel wireless reconfigurable processor architecture and programming

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Volumn , Issue , 2003, Pages

  Sarrigeorgidis, Konstantinos ^a   Rabaey, Jan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DISTRIBUTED PARAMETER NETWORKS; ENERGY EFFICIENCY; ENERGY UTILIZATION; FLOW GRAPHS; INTEGRATED CIRCUIT DESIGN; MATRIX ALGEBRA; NETWORK ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; RECONFIGURABLE ARCHITECTURES; WIRELESS TELECOMMUNICATION SYSTEMS;

DESIGN METHODOLOGY; ENERGY CONSUMPTION MODEL; MASSIVELY PARALLELS; MATRIX COMPUTATION; PROCESSOR ARCHITECTURES; PROPOSED ARCHITECTURES; RECONFIGURABLE PROCESSORS; WIRELESS COMMUNICATION ALGORITHMS;

PARALLEL ARCHITECTURES;

EID: 33749563000     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213313     Document Type: Conference Paper

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10. K. Sarrigeorgidis "Massively Parallel Reconfigurable Wireless Processor Architecture and Programming " Ph. D Thesis, U. C. Berkeley, Dec, 2002