On the passivation of interface states in SONOS test structures: Impact of device layout and annealing process

IEEE International Conference on Microelectronic Test Structures

Volumn 2006, Issue , 2006, Pages 51-55

  Driussi, F ^a   Selmi, L ^a   Akil, N ^b   Van Duuren, M J ^b   Van Schaijk, R ^b  

^a UNIVERSITY OF UDINE   (Italy)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

GATE STACKS; HYDROGEN ANNEAL; HYDROGEN PASSIVATION; INTERFACE STATES;

ANNEALING; CHEMICAL BONDS; INTERFACES (MATERIALS); PASSIVATION; SILICA; SILICON NITRIDE;

GATES (TRANSISTOR);

EID: 33749535444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2006.1614274     Document Type: Conference Paper

References (7)

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7. G. Groeseneken, H.Maes, N.Beltran and R.F.De Keersmaecker, "A Reliable Approach to Charge-Pumping Measurements in MOS Transistors", IEEE Transaction on Electron Devices, vol. 31, n. 1 p. 42, 1984.