Hardware architecture for booth-barrett's modular multiplication

International Journal of Modelling and Simulation

Volumn 26, Issue 3, 2006, Pages 183-189

  Nedjah, N ^a   Mourelle, L M ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

Barrett algorithm; Booth algorithm; Cryptosystems; Modular multiplication

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC;

BARRETT ALGORITHM; BOOTH ALGORITHM; MODULAR MULTIPLICATION; OPERANDS;

PUBLIC KEY CRYPTOGRAPHY;

EID: 33749419489     PISSN: 02286203     EISSN: None     Source Type: Journal    
DOI: 10.1080/02286203.2006.11442367     Document Type: Article

References (18)

1. R. Rivest, A. Shamir, & L. Adleman, A method for obtaining digital signature and public-key cryptosystems, Comm. ACM, 21, 1978, 120-126.
2. E.F. Brickell, A survey of hardware implementation of RSA, Proc. CRYPTO'98 (Lecture Notes in Computer Science 435) (Santa Barbara, CA: Springer-Verlag, 1989), 368-370.
3. C.D. Walter, Systolic modular multiplication, IEEE Trans. on Computers, 42(3), 1993, 376-378.
4. S.E. Eldridge & C.D. Walter, Hardware implementation of Montgomery's modular multiplication algorithm, IEEE Trans. on Computers, 42(6), 1993, 619-624.
5. Ç.K. Koç, High-speed RSA implementation, Technical report, RSA Laboratories, RSA Data Security, Inc., Redwood City, CA, November 1994.
6. G.R. Blakley, A computer algorithm for the product AB modulo M, IEEE Trans. on Computers, 32(5), 1983, 497-500.
7. P.L. Montgomery, Modular multiplication without trial division, Mathematics of Computation, 44, 1984, 519-521.
8. N. Nedjah & L. de Macedo Mourelle, Fast reconfigurable systolic hardware for modular multiplication and exponentiation, Journal of Systems Architecture, 49, 2003, 387-396.
9. J. Rabaey, Digital integrated circuits: A design perspective (Englewood Cliffs, NJ: Prentice-Hall, 1995).
10. A. Booth, A signed binary multiplication technique, Journal of Mechanics and Applied Mathematics, 4, 1951, 236-240.
11. O. MacSorley, High-speed arithmetic in binary computers, Proc. IEEE, Los Alamitos, CA, 1961, 67-91.
12. G.W. Bewick, Fast multiplication algorithms and implementation, doctoral diss., Department of Electrical Engineering, Stanford University, 1994.
13. P. Barrett, Implementing the Rivest, Shamir and Aldham public-key encryption algorithm on standard digital signal processor, Proc. CRYPTO'86 (Lecture Notes in Computer Science 263) (Santa Barbara, CA: Springer-Verlag, 1986), 311-323.
14. V. Shindler, High-speed RSA hardware, based on low-power pipelined logic, doctoral diss., Institut für Angewandte Information-sverarbeitung und Kommunikations-technologie, Technishe Universität Graz, 1997.
15. C.D. Walter, A verification of Brickell's fast modular multiplication algorithm, International Journal of Computer Mathematics, 33, 1990, 153-169.
16. Z. Navabi, VHDL: Analysis and modeling of digital systems, 2nd ed. (New York, NY: McGraw Hill, 1998).
17. MyCad, Inc. & Seodu Logic, Inc., MyVHDL Station V 4.0 Tutorial, http://www.mycad.com or http://www.mycad.co.kr.
18. Xilinx™, Foundations Series Software, http://www.xilinx.com.