Low-power systolic array processor architecture for FSBM video motion estimation

Electronics Letters

Volumn 42, Issue 20, 2006, Pages 1146-1148

  Jiang, M ^a   Crookes, D ^a   Davidson, S ^a   Turner, R ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MOTION ESTIMATION; PARALLEL PROCESSING SYSTEMS; SWITCHING; VIDEO SIGNAL PROCESSING;

FULL SEARCH BLOCK MATCHING (FSBM); PARTIAL DISTORTION ELIMINATION ALGORITHMS; POWER CONSUMPTION; SYSTOLIC ARRAY PROCESSORS;

SYSTOLIC ARRAYS;

EID: 33749345463     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20061972     Document Type: Article

References (6)

1. ISO/IEC JTC1/SC29/WG11, MPEG-4 Visual Final Committee Draft, Dublin, Ireland July 1998
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3. Brunig, M., and Niehsen, W.: ' Fast full-search block matching ', IEEE Trans. Circuits Syst. Video Technol., 2001, 11, (2), p. 241-247 10.1109/76.905989 1051-8215
4. Huang, Y., Chien, S., Hsieh, B., and Chen, L.: ' Global elimination algorithm and architecture design for fast block matching motion estimation ', IEEE Trans. Circuits Syst. Video Technol., 2004, 14, (6), p. 898 10.1109/TCSVT.2004.828321 1051-8215
5. Huang, H.C., and Hung, Y.P.: ' Adaptive early jump-out technique for fast motion estimation in video coding ', Graph. Models Image Process., 1997, 59, (6), p. 388 10.1006/gmip.1997.0449 1077-3169
6. Do, V.L., and Yun, K.Y.: ' A low-power VLSl architecture for full-search block-matching motion estimation ', IEEE Trans. Circuits Syst. Video Technol., 1998, 8, (4), p. 393 10.1109/76.709406 1051-8215