Data dependence analysis and bit-level systolic arrays of the median filter

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 8, Issue 8, 1998, Pages 1015-1024

  Yang, Dyi Long ^a   Chen, Chin Hsing ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Bit level systolic array; Data dependence; Delete and insert sort algorithm; Median filter

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SYSTOLIC ARRAYS; THROUGHPUT; VLSI CIRCUITS;

DATA DEPENDENCE ANALYSIS; DELETE AND INSERT SORT ALGORITHM; MEDIAN FILTER;

DIGITAL FILTERS;

EID: 0032266818     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.736737     Document Type: Article

References (24)

1. A. K. Jain, Fundamentals of Digital Image Processing. New York: Prentice-Hall, 1989.
2. D. S. Richards, "VLSI median filters," IEEE Trans. Acoust., Speech, Signal Processing, vol. 38, no. 1, pp. 145-153, Jan. 1990.
3. D. H. Kang, J. H. Choi, Y. H. Lee, and C. Lee, "Applications of a DPCM system with median predictors for image coding," IEEE Trans. Consumer Electronics, vol. 38, no. 3, pp. 429-435, Aug. 1992.
4. H. Rantanen, M. Karlsson, P. Pohjala, and S. Kalli, "Color video signal processing with median filters," IEEE Trans. Consumer Electron., vol. 38, no. 3, pp. 157-161, Aug. 1992.
5. T. Viero, K. Oistamo, and Y. Neuvo, "Three-dimensional median-related filters for color image sequence filtering," IEEE Trans. Circuits Syst. Video Technol., vol. 4, no. 2, pp. 129-142, Apr. 1994.
6. L. A. Christopher, W. T. Mayweather III, and S. S. Perlman, "A VLSI median filter for impulse noise elimination in composite or component TV signals," IEEE Trans. Consumer Electron., vol. 34. pp. 262-267, 1988.
7. X. Song, L. Yin, and Y. Neuvo, "Image sequence coding using adaptive weighted median prediction," in Proc. Signal Processing VI, EUSIPCO-92, Brussels, Aug. 1992, pp. 1307-1310.
8. K. Oistamo and Y. Neuvo, "A motion insensitive method for scan rate conversion and cross error cancellation," IEEE Trans. Consumer Electron., vol. 37, pp. 296-302, Aug. 1991.
9. M. Karaman, L. Onural, and A. Atalar, "Design and implementation of a general-purpose median filter unit in CMOS VLSI," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 505-513, Apr. 1990.
10. O. Yli-Harja, J. Astola, and Y. Neuvo, "Analysis of the properties of median and weighted median filters using threshold logic and stack filter representation," IEEE Trans. Signal Processing, vol. 39, no. 2, pp. 395-410, Feb. 1991.
11. J. P. Fitch, "Software and VLSI algorithms for generalized rank-order filtering," IEEE Trans. Circuits Syst., vol. CAS-34, no. 5, pp. 553-559, May 1987.
12. J. P. Fitch, E. J. Coyle, and N. C. Gallagher Jr., "Median filtering by threshold decomposition," IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, no. 6, pp. 1183-1188, Dec. 1984.
13. J. P. Fitch, E. J. Coyle, and N. C. Gallagher Jr., "Threshold decomposition of multidimensional ranked order operations," IEEE Trans. Circuits Syst., vol. CAS-32, no. 5, pp. 445-450, May 1985.
14. C. Chakrabarti, "Sorting network based architectures for median filters," IEEE Trans. Circuits, and Syst. II, vol. 40, no. 11, pp. 723-727, Nov. 1993.
15. L. E. Lucke and K. K. Parhi, "Parallel processing architectures for rank order and stack filters," IEEE Trans. Signal Processing, vol. 42, no. 5, pp. 1178-1189, May 1994.
16. I. Pitas, "Fast algorithms for running ordering and max/min calculation," IEEE Trans. Circuits Syst., vol. 36, no. 6, pp. 795-804, June 1989.
17. C. Y. Lee, P. W. Hsieh, and J. M. Tsai, "High-speed median filter designs using shiftable content-addressable memory," IEEE Trans. Circuits Syst. Video. Technol., vol. 4, no. 6, pp. 544-549, Dec. 1994.
18. R. Roncella, R. Saletti, and P. Terreni, "70-MHz 2-μm CMOS bit-level systolic array median filter," IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 530-536, May 1993.
19. G. R. Arce and P. J. Warter, "A median filter architecture suitable for VLSI implementation," in Proc. 23rd Ann. Allerton Conf. Communication, Control, and Computing, 1984, pp. 172-181.
20. C. Chakrabarti, "High sample rate systolic architectures for median filters," in Proc. ISCAS'92, San Diego, CA, May 10-13, 1992, pp. 1073-1076.
21. K. Chen, "Bit-serial realizations of a class of nonlinear filters based on positive Boolean functions," IEEE Trans. Circuits Syst., vol. 36, no. 6, pp. 785-794, June 1989.
22. C. L. Lee and C. W. Jen, "Bit-sliced median filter design based on majority gate," Proc. Inst. Electron. Eng., pt. G, Feb. 1992, vol. 139, no. 1, pp. 63-71.
23. L. W. Chang and J. H. Lin, "A bit-level systolic array for median filter," IEEE Trans. Signal Processing, vol. 40, no. 8, Aug. 1992.
24. S. Y. Kung, VLSI Array Processors. New York: Prentice-Hall, 1988.