A low-power 2-GSample/s comparator in 120 nm CMOS technology

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 507-510

  Goll, Bernhard ^a   Zimmermann, Horst ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MOSFET DEVICES; NATURAL FREQUENCIES; POWER CONTROL; SIGNAL PROCESSING; THRESHOLD VOLTAGE;

CHARGE INJECTION; COMPARATOR STRUCTURES; OUTPUT VOLTAGE; POWER CONSUMPTION;

COMPARATOR CIRCUITS;

EID: 33749160105     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541671     Document Type: Conference Paper

References (8)

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