FPGA-based hardware acceleration on I/O-bound scientific applications

WSEAS Transactions on Computers

Volumn 5, Issue 12, 2006, Pages 2977-2983

  Lo, Chia Tien Dan ^a   Tai, Yi Gang ^a   Psarris, Kleanthis ^a  

^a University of Texas at San Antonio   (United States)

Author keywords

Blocked algorithms; FPGA; Loop optimization; QR decomposition; Reconfigurable computing

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SIMULATION; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION;

BLOCKED ALGORITHMS; LOOP OPTIMIZATION; QR DECOMPOSITION; RECONFIGURABLE COMPUTING;

NATURAL SCIENCES COMPUTING;

EID: 33749076879     PISSN: 11092750     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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