SCOPUS 정보 검색 플랫폼

ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings

Volumn 1, Issue , 2005, Pages 103-106

Automated design of FFT/IFFT processors for advanced telecom applications

(4) Saponara, Sergio a Serafini, Luca a Fanucci, Luca a Terreni, Pierangelo a

a UNIVERSITY OF PISA (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA PROCESSING; FAST FOURIER TRANSFORMS; LOGIC DESIGN; WIRELESS TELECOMMUNICATION SYSTEMS;

ARCHITECTURE PARAMETERS; AUTOMATED DESIGN; C++; PARAMETRIC CASCADE ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 33749062350 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISSCS.2005.1509861 Document Type: Conference Paper

Times cited : (2)

References (10)

1
- 0036904659
- A short overview of the VDSL system requirements
- M. Nava, C. Del Toso, "A short overview of the VDSL system requirements", IEEE Comm. Magazine, vol. 40, pp. 82-90, 2002
- (2002) IEEE Comm. Magazine , vol.40 , pp. 82-90
- Nava, M.¹ Del Toso, C.²

2
- 33749078135
- MultiBand OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a, Sept.
- MultiBand OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a, Sept. 2004, available from www.multibandofdm.org
- (2004)

3
- 0036898051
- FAST: FFT ASIC automated synthesis
- L. Fanucci, M. Forliti, P. Terreni, "FAST: FFT ASIC automated synthesis", Integration the VLSI Journal, vol. 33, pp. 23-37, 2003
- (2003) Integration the VLSI Journal , vol.33 , pp. 23-37
- Fanucci, L.¹ Forliti, M.² Terreni, P.³

4
- 0032677870
- Rapid design of application specific FFT cores
- J. Ding, J.V. McCanny, Y. Hu, "Rapid design of application specific FFT cores". IEEE Trans Signal Process., vol. 47, pp. 1371-1381, 1999
- (1999) IEEE Trans Signal Process. , vol.47 , pp. 1371-1381
- Ding, J.¹ McCanny, J.V.² Hu, Y.³

5
- 0032675914
- COBRA: 100-MOPS single-chip programma ble expandable FFT
- T. Chen, G. Sunada, J. Jin, "COBRA: 100-MOPS single-chip programma ble expandable FFT", IEEE Tran. VLSI Syst., vol. 7, pp. 174-182, 1999
- (1999) IEEE Tran. VLSI Syst. , vol.7 , pp. 174-182
- Chen, T.¹ Sunada, G.² Jin, J.³

6
- 0032218295
- Design and implementation of an FFT processor for VDSL
- M. Rudberg, M. Sandberg, K. Ekholm, ''Design and implementation of an FFT processor for VDSL", Proc. IEEE APCCS'98, pp. 611-614, 1998
- (1998) Proc. IEEE APCCS'98 , pp. 611-614
- Rudberg, M.¹ Sandberg, M.² Ekholm, K.³

7
- 0024915503
- A pipelined FFT processor for word-sequential data
- G. Bi, E. Jones, "A pipelined FFT processor for word-sequential data", IEEE Trans. Aco., Speech, Signal Proc., vol. 37, pp. 1982-1985, 1989
- (1989) IEEE Trans. Aco., Speech, Signal Proc. , vol.37 , pp. 1982-1985
- Bi, G.¹ Jones, E.²

8
- 0031629888
- A 9.5 mW 330 μs 1024-point FFT processor
- B. M. Baas, "A 9.5 mW 330 μs 1024-point FFT processor", Proc. IEEE CICC'98, pp. 127-130, 1998
- (1998) Proc. IEEE CICC'98 , pp. 127-130
- Baas, B.M.¹

9
- 0019548997
- Fixed point error analysis of radix-4 FFT
- V. Prakash, V. Rao, "Fixed point error analysis of radix-4 FFT", Signal Processing, vol. 3, pp. 123-133, 1981
- (1981) Signal Processing , vol.3 , pp. 123-133
- Prakash, V.¹ Rao, V.²

10
- 0030372973
- Error analysis of FFT architectures for digital video applications
- C. Hui, T. Ding, J. McCanny et al., "Error analysis of FFT architectures for digital video applications", Proc. IEEE ICECS'96, pp. 820-823, 1996
- (1996) Proc. IEEE ICECS'96 , pp. 820-823
- Hui, C.¹ Ding, T.² McCanny, J.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.