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Volumn 3985 LNCS, Issue , 2006, Pages 335-346

Updates on the security of FPGAs against power analysis attacks

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CORRELATION METHODS; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; MICROELECTRONICS; PRODUCT DESIGN; SPURIOUS SIGNAL NOISE;

EID: 33748999531     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11802839_42     Document Type: Conference Paper
Times cited : (31)

References (16)
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    • Brier, E.1    Clavier, C.2    Olivier, F.3
  • 4
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    • Template attacks
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    • Chari, S.1    Rao, J.2    Rohatgi, P.3
  • 5
    • 35248893001 scopus 로고    scopus 로고
    • True random number generator embedded in reconfigurable hardware
    • the proceedings of CHES 2002 Redwood Shores, California, USA, August
    • V. Fischer, M. Drutarovsky, True Random Number Generator Embedded in Reconfigurable Hardware, in the proceedings of CHES 2002, Lecture Notes in Computer Science, vol 2523, pp 415-430, Redwood Shores, California, USA, August 2002.
    • (2002) Lecture Notes in Computer Science , vol.2523 , pp. 415-430
    • Fischer, V.1    Drutarovsky, M.2
  • 6
    • 84939573910 scopus 로고    scopus 로고
    • Differential power analysis
    • the proceedings of Cypto 1999, Santa-Barbara, USA, August Springer-Verlag
    • P. Kocher, J. Jaffe, B. Jun, Differential Power Analysis, in the proceedings of Cypto 1999, Lecture Notes in Computer Science, vol 1666, pp 398-412, Santa-Barbara, USA, August 1999, Springer-Verlag.
    • (1999) Lecture Notes in Computer Science , vol.1666 , pp. 398-412
    • Kocher, P.1    Jaffe, J.2    Jun, B.3
  • 7
    • 34248682000 scopus 로고
    • FIPS PUB 46, the data encryption standard
    • NIST, U.S. Dept. of Commerce, Jan
    • National Bureau of Standards, FIPS PUB 46, The Data Encryption Standard, Federal Information Processing Standard, NIST, U.S. Dept. of Commerce, Jan 1977.
    • (1977) Federal Information Processing Standard
  • 8
    • 0003508558 scopus 로고    scopus 로고
    • FIPS 197, advanced encryption standard
    • NIST, U.S. Dept. of Commerce, November
    • National Bureau of Standards, FIPS 197, Advanced Encryption Standard, Federal Information Processing Standard, NIST, U.S. Dept. of Commerce, November 2001.
    • (2001) Federal Information Processing Standard
  • 9
    • 33746619365 scopus 로고    scopus 로고
    • A comparative cost/security analysis of fault attack countermeasures
    • Edinburgh, Scotland, September
    • T.G. Malkin, F.-X. Standaert, M. Yung, A Comparative Cost/Security Analysis of Fault Attack Countermeasures, in the proceedings of FDTC 2005, Edinburgh, Scotland, September 2005.
    • (2005) The Proceedings of FDTC 2005
    • Malkin, T.G.1    Standaert, F.-X.2    Yung, M.3
  • 10
    • 35248847436 scopus 로고    scopus 로고
    • Power-analysis attacks on an FPGA - First experimental results
    • the proceedings of CHES 2003, Cologn, Germany, September, Springer-Verlag
    • S.B. Ors, E. Oswald, B. Preneel, Power-Analysis Attacks on an FPGA - First Experimental Results, in the proceedings of CHES 2003, Lecture Notes in Computer Science, vol 2279, pp 35-50, Cologn, Germany, September 2003, Springer-Verlag.
    • (2003) Lecture Notes in Computer Science , vol.2279 , pp. 35-50
    • Ors, S.B.1    Oswald, E.2    Preneel, B.3
  • 11
    • 33749029794 scopus 로고    scopus 로고
    • Power and electromagnetic analysis: Improved model, consequences and comparisons
    • to appear in Integration, Spring, Elsevier
    • E. Peeters, F.-X. Standaert, J.-J. Quisquater, Power and Electromagnetic Analysis: Improved Model, Consequences and Comparisons, to appear in Integration, the VLSI Journal, Spring 2006, Elsevier.
    • (2006) The VLSI Journal
    • Peeters, E.1    Standaert, F.-X.2    Quisquater, J.-J.3
  • 13
    • 0036384096 scopus 로고    scopus 로고
    • Dynamic power consumption in virtex-2 FPGA family
    • Monterey, California, USA, February
    • L. Shang, A. Kaviani, K. Bathala, Dynamic Power Consumption in Virtex-2 FPGA Family, in the proceedings of FPGA 2002, pp 157-164, Monterey, California, USA, February 2002.
    • (2002) The Proceedings of FPGA 2002 , pp. 157-164
    • Shang, L.1    Kaviani, A.2    Bathala, K.3
  • 14
    • 24744465637 scopus 로고    scopus 로고
    • Power analysis of an FPGA implementation of rijndael: Is pipelining a DPA countermeasure?
    • the proceedings of CHES 2004, Cambridge, MA, USA, August
    • F.-X. Standaert, S.B. Ors, B. Preneel, Power Analysis of an FPGA Implementation of Rijndael: Is Pipelining a DPA Countermeasure?, in the proceedings of CHES 2004, Lecture Notes in Computer Science, vol 3156, pp 30-44, Cambridge, MA, USA, August 2004.
    • (2004) Lecture Notes in Computer Science , vol.3156 , pp. 30-44
    • Standaert, F.-X.1    Ors, S.B.2    Preneel, B.3
  • 15
    • 33748988330 scopus 로고    scopus 로고
    • Power analysis attacks and countermeasures of field programmable gate arrays: Recent results
    • to appear special issue on Cryptographic Hardware and Embedded Systems, Spring
    • F.-X. Standart, E. Peeters, G. Rouvroy, J.-J. Quisquater, Power Analysis Attacks and Countermeasures of Field Programmable Gate Arrays: Recent Results, to appear in the Proceedings of the IEEE, special issue on Cryptographic Hardware and Embedded Systems, Spring 2006.
    • (2006) The Proceedings of the IEEE
    • Standart, F.-X.1    Peeters, E.2    Rouvroy, G.3    Quisquater, J.-J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.