Increasing the cache efficiency by eliminating noise

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2006, Issue , 2006, Pages 145-156

  Pujara, Prateek ^a   Aggarwal, Aneesh ^a  

^a State University of New York at Binghamton   (United States)

Author keywords

Block Size; Cache Noise; Cache Organization; Hardware Prefetching; Spatial Locality

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; DATA PROCESSING; ENERGY MANAGEMENT; ENERGY UTILIZATION; PERSONAL COMPUTERS;

BLOCK SIZES; CACHE NOISE; CACHE ORGANIZATION; HARDWARE PREFETCHING; SPATIAL LOCALITY;

SPURIOUS SIGNAL NOISE;

EID: 33748863143     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598121     Document Type: Conference Paper

References (22)

1. M. Bekerman, et. al., Correlated Load Address Predictors, Proc. ISCA-26, 1999.
2. D. Burger, et. al., Memory bandwidth limitations of future microprocessors, Proc. ISCA-23, 1996.
3. D. Burger and T. Austin, The SimpleScalar Tool Set, Version 2.0, Computer Arch. News, 1997.
4. A. Dhodapkar and J. Smith, Comparing Program Phase Detection Techniques, Proc. Micro-36, 2003.
5. C. Dubnicki and T. LeBlanc, Adjustable block size coherent caches, Proc. ISCA-19, 1992.
6. J. Gonzalez and A. Gonzalez, Speculative execution via address prediction and data prefetching, Proc. ICS, 1997.
7. M. Hill and A. Smith, Experimental evaluation of on-chip microprocessor cache memories, Proc. ISCA-11, 1984.
8. A. Huang and J. Shen, A limit study of local memory requirements using value reuse profiles, Micro-28, 1995.
9. K. Inoue, et. al., Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs, Proc. HPCA, 1999.
10. T. Johnson and W. Hwu, Run-time adaptive cache hierarchy management via reference analysis, Proc. ISCA-24, 1997.
11. T. Johnson, et. al., Run-time spatial locality detection and optimization, Proc. Micro-30, 1997.
12. S. Kumar and C. Wilkerson, Exploiting spatial locality in data caches using spatial footprints, Proc. ISCA-25, 1998.
13. G. McNiven and E. Davidson, Analysis of memory referencing behavior for design of local memories, Proc. ISCA-15, 1988.
14. D. Nicolaescu, et. al., Compiler-directed Cache Line Size Adaptivity, IMS, 2000.
15. S. Przybylski, The performance impact of block sizes and fetch strategies, Proc. ISCA-20, 1993.
16. A. Seznec, Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio, Proc. ISCA-21, 1994.
17. A. Smith, Line(block) size choice for cpu cache memories, ACM Transactions on Computer Systems, C-36:1063-1075, 1987.
18. A. Veidenbaum, et. al., Adapting Cache Line Size to Application Behavior, Proc. ICS, 1999.
19. E. Witchel and K. Asanovic, The Span Cache: Software Controlled Tag Checks and Cache Line Size, Proc. ISCA-28, 2001.
20. C. Zhang, et. al., Energy Benefits of a Configurable Line Size Cache for Embedded Systems, Proc. Int'l Symp. on VLSI, 2003.
21. C. F. Chen et al., Accurate and complexity-effective spatial pattern prediction, Proc. HPCA-10, 2004.
22. P. Shivakumar and N. Jouppi, CACTI 3.0: An Integrated Cache timing, Power, and Area Model, Technical Report, DEC Western Lab, 2002.