Biasing techniques for subthreshold MOS resistive grids

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2164-2167

  Wee, Keng Hoong ^a   Sit, Ji Jon ^a   Sarpeshkar, Rahul ^a  

^a Massachusetts Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIASING TECHNIQUES; CMOS PROCESS; DYNAMIC RANGE; INPUT CURRENT; LINEAR OPERATIONS; MOS CIRCUITS; MOS TRANSISTORS; NON-LINEARITY; RESISTIVE GRID; RESISTIVE NETWORK; SOURCE BIASING; SOURCE VOLTAGE; SPATIAL FILTERING; SUBTHRESHOLD; WIDE DYNAMIC RANGE;

TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

LINEARIZATION;

EID: 33748368991     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465049     Document Type: Conference Paper

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