A Metric for Automatic Word-Length Determination of Hardware Datapaths

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 2228-2231

  Cantin, M A ^a   Savaria, Y ^a   Prodanos, D ^b   Lavoie, P ^b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b DEFENCE RESEARCH AND DEVELOPMENT CANADA   (Canada)

Author keywords

Automatic determination; Floating point to fixed point conversion; Metric, optimization; Word length

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; DATA STRUCTURES; ERROR DETECTION; MATHEMATICAL MODELS; OPTIMIZATION; TEXT PROCESSING;

AUTOMATIC DETERMINATION; FLOATING-POINT TO FIXED-POINT CONVERSION; METRIC; WORD LENGTH;

WORD PROCESSING;

EID: 33748302175     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.862733     Document Type: Article

References (22)

1. H. Keding, M. Willems, M. Coors, and H. Meyr, "FRIDGE: A fixed-point design and simulation environment," in Proc. Design, Automation and Test Europe, Paris, France, 1998, pp. 429-4-35.
2. M.-A. Cantin, Y. Blaquière, Y. Savaria, P. Lavoie, and E. Granger, "Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Geneva, Switzerland, 2000, vol. 3, pp. 141-144.
3. M.-A. Cantin, S. Regimbai, S. Catudal, and Y. Savaria, "A unified environment to access image quality," J. Circuits Syst. Comput, vol. 13, no. 6, pp. 1289-1306, 2004.
4. J. Yli-Kaakinen and T. Saramaki, "An efficient algorithm for the design of lattice wave digital filters with short coefficient wordlength," in Proc. Int. Symp. Circuits and Systems, Orlando, FL, May 1999, vol. 3, pp. 443-448.
5. I.-T. Lim and J. Bahn, "Optimal wordlength determination of AC-3 decoding hardware based on fixed-point analysis and simulations of AC-3 algorithm," in Proc. IEEE Workshop Signal Processing, Leicester, U.K, Nov. 1997, pp. 301-310.
6. T. Aamodt, "Floating-point to fixed-point compilation and embedded architectural support," M.S. thesis, Dept. Elect. Comput. Eng. Univ, Toronto, Toronto, ON, Canada, 2001.
7. H. Yamashita, H. Yasuura, F. N. Eko, and C. Yun, "Variable size analysis and validation of computation quality," in Proc. Workshop High-level Design Validation and Test (HLDVT), Berkeley, CA, Nov. 2000, pp. 95-100.
8. S.A. Wadekar, "Accuracy sensitive word-length selection for algorithm optimization," in Proc. Int. Conf. Computer Design: VLSI Computers and Processors (ICCD), Austin, TX, 1998, pp. 54-61.
9. S. Kim, K.-I. Kum, and W. Sung, "Fixed-point optimization utility for C and C++ based digital signal processing programs," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 45, no. 11, pp. 1455-1464, Nov. 1998.
10. R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, and I. Bolsens, "A methodology and design environment for DSP ASIC fixed point refinement," in Proc. Design, Automation and Test Europe Conf. and Exhibition, Munich, Germany, 1999, pp. 271-276.
11. Press Release: Synopsys Accelerates System-Level C-Based DSP Design With CoCentric Fixed-Point Designer Tool Synopsys Inc, 2000.
12. W. Sung and K. Kum, "Simulation-based word-length optimization method for fixed-point digital signal processing systems," IEEE Trans. Signal Process, vol. 43, no. 12, pp. 3087-3090, Dec. 1995.
13. K. Han, I. Eo, K. Kim, and H. Cho, "Numerical word-length optimization for CDMA demodulator," in Proc. IEEE Int. Symp. Circuits and Systems, Sydney, Australia, 2001, vol. 4, pp. 290-293.
14. H. Choi and W. P. Burleson, "Search-based wordlength optimization for VLSI/DSP synthesis," in Proc. VLSI Signal Processing, La Jolla, CA, 1994, pp. 198-207.
15. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671-680, May 1983.
16. P. D. Fiore and L. Lee, "Closed-form and real-time wordlength adaptation," in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, Phoenix, AZ, 1999, vol. 4, pp. 1897-1900.
17. M.-A. Cantin, Y. Savaria, and P. Lavoie, "A comparison of automatic word length optimization procedures," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Phoenix-Scottsdale, AZ, 2002, vol. 2, pp. 612-615.
18. IEEE Standard Specifications for the Implementations of 8 × S Inverse Discrete Cosine Transform, IEEE Std 1180-1990, CAS Standards Committee of the IEEE Circuits and Systems Society, 1991.
19. L. Claesen, F. Catthoor, D. Lanneer, G. Goossens, S. Note, J. Van Meerbergen, and H. De Man, "Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers," in Proc. IEEE Custom Integrated Circuits Conf, Rochester, NY, 1988, pp. 14.7.1-14.7.4.
20. M.-A. Cantin, Y. Savaria, D. Prodanos, and P. Lavoie, "An automatic word length determination method," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Sydney, Australia, 2001, vol. 5, pp. 53-56.
21. K. Kota and J. R. Cavallaro, "Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors," IEEE Trans. Comput, vol. 42, no. 7, pp. 769-779, Jul. 1993.
22. S. Catudal, M.-A. Cantin, and Y. Savaria, "Performance driven validation applied to video processing," WSEAS Trans. Electron, vol. 1, no. 3, pp. 568-575, Jul. 2004.