A 10.7-MHz sixth-order SC ladder filter in 0.35-μm CMOS technology

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 8, 2006, Pages 1625-1635

  Adut, Jozef ^a   Silva Martinez, Jose ^a   Rocha Perez, Miguel ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Capacitive reduction techniques; Fast operational transconductance amplifiers (OTAs); High Q switched capacitor (SC) filters; SC filters

Indexed keywords

BANDPASS FILTERS; ELECTRIC DISTORTION; INTEGRATED CIRCUIT LAYOUT; INTERMODULATION MEASUREMENT; LADDER NETWORKS; MOS CAPACITORS; OPERATIONAL AMPLIFIERS; SIGNAL TO NOISE RATIO;

CAPACITIVE REDUCTION TECHNIQUES; OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTAS); SWITCHED-CAPACITOR FILTER;

CMOS INTEGRATED CIRCUITS;

EID: 33747849297     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.879070     Document Type: Article

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