Local resistance measurement across grain boundaries in low-temperature polycrystalline silicon layer of thin film transistor using scanning spreading resistance microscopy

Applied Physics Letters

Volumn 89, Issue 6, 2006, Pages

  Yamagiwa, Hiroto ^a   Abo, Satoshi ^a   Wakaya, Fujio ^a   Takai, Mikio ^a   Sakamoto, Tadao ^b   Tokioka, Hidetada ^b   Nakagawa, Naoki ^b  

^a OSAKA UNIVERSITY   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; GRAIN BOUNDARIES; POLYSILICON; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DOPING; THERMAL EFFECTS;

DRAIN; LIGHTLY DOPED DRAIN (LDD); RESISTANCE MICROSCOPY; SCANNING SPREADING RESISTANCE MICROSCOPY;

THIN FILM TRANSISTORS;

EID: 33747109850     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2266451     Document Type: Article

References (6)

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