Pipelined operation of image capturing and processing

2005 5th IEEE Conference on Nanotechnology

Volumn 1, Issue , 2005, Pages 275-278

  Chang, Chi Jeng ^a   Huang, Zen Yi ^a   Li, Hsin Yen ^a   Hu, Kai Ting ^a   Tseng, Wen Chih ^a  

^a NATIONAL TAIWAN NORMAL UNIVERSITY   (Taiwan)

Author keywords

2 D convolver; 2 D sorter; Bubble sorting; CMOS image sensor; Digital image processing; FPGA

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONVOLUTION; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; IMAGE QUALITY; PIPELINE PROCESSING SYSTEMS;

2-D CONVOLVER; 2-D SORTER; BUBBLE SORTING; IMAGE NOISES;

IMAGE SENSORS;

EID: 33746971002     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2005.1500749     Document Type: Conference Paper

References (4)

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3. Maheshwari R., Rao S.S.S.P., and Poonacha P.G., "FPGA implementation of median filter," Tenth International Conference on VLSI Design, June, 1997, pp. 523 -524.
4. Benkrid K., Crookes D., and Benkrid A., "Towards a general framework for FPGA based image processing using hardware skeleton," Parallel Computing vol. 28, Issue: 7-8, Aug, 2002, pp. 1141-1154.