Design and implementation of a high level programming environment for FPGA-based image processing

IEE Proceedings: Vision, Image and Signal Processing

Volumn 147, Issue 4, 2000, Pages 377-384

  Crookes, D ^a   Benkrid, K ^a   Bouridane, A ^a   Aiotaibi, K ^a   Benkrid, A ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA STRUCTURES; FIELD PROGRAMMABLE GATE ARRAYS; HIGH LEVEL LANGUAGES; MATHEMATICAL MODELS; USER INTERFACES;

HIGH LEVEL IMAGE PROCESSING COPROCESSORS; RECONFIGURABLE HARDWARES;

DIGITAL SIGNAL PROCESSING;

EID: 0034245247     PISSN: 1350245X     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-vis:20000579     Document Type: Article

References (23)

1. WEBBER, U.C. (Ed.): 'Image processing and transputers' (IOS Press, 1992)
2. RAJAN, K., SANGUNNI, K.S., and RAMAKRISHNA, J.: 'Dual-DSP systems for signal and image-processing', Microprocess. Microsyst., 1993, 17, (9), pp. 556-560
3. AKIYAMA, T., AONO, H., and AOKI, K.et al.: 'MPEG2 video codec using image compression DSP', IEEE Trans. Consum. Electron., 1994, 40, (3), pp. 466-472
4. CHRISTOPHER, L.A., MAYWEATHER, W.T., and PERLMAN, S.S.: 'VLSI median filter for impulse noise elimination in composite or component TV sienals', IEEE Trans. Consum. Electron., 1988,34, (1), pp. 263-267
5. ROSE, J., and SANGIOVANNI-VINCENTELLI, A.: 'Architecture of field programmable gate arrays', Proc. IEEE, 1993,81, (7), pp. 10131029
6. http:/Avww.xilinx.corri/products/virtex/ss-vir.htm
7. ARNOLD, J.M., BUELL, D.A., and DAVIS, E.G.: 'Splash-2'. Proceedings of 4th annual ACM symposium on Parallel algorithms and architectures, June 1992 (ACM Press, 1992) pp. 316-324
8. Gigaops Ltd.:,'The G-800 system' (2374 Eunice St. Berkeley, CA 94708)
9. http://www.vcc.com/
10. ftp://ftp.digital.corn/pub/DEC/SRC/publications/ludwig/FPL99 LudwigSinghSlous.pdf
11. http:/Avww.synopsys.com/news/pubs/snug/snug99.papers/ Jaffer-FinaI.pdf
12. HUTCHINGS, B., BELLOWS, P., HAWKINS, J., HEMMERT, S., NELSON, B., and RYTTING, M.: 'A CAD suite for high-performance FPGA design'. Preliminary proceedings of FCCM'99,
13. http://www.xilinx.com/partinfo/4kconf.pdf
14. RITTER, G.X., WILSON, J.N., and DAVIDSON, J.L.: 'Image algebra: an overview, Comput. Vis. Graph. Image Pmcess., 1990, 49, pp. 297331
15. SHOUP, R.G.: 'Parameterised convolution filtering in an FPGA', in MOORE, W, and LUK, W. (Eds.): 'More FPGAs' (EE&CS Books, Abington, 1994), p. 274
16. KAMP, W, KUNEMUND, H., SOLDNER, and HOFER, H.: 'Programmable 2D linear filter for video applications', IEEEJ. SolidState Circuits, 1990, pp. 735-740
17. AVIZIENIS, A.: 'Sisned digit number representation for fast parallel arithmetic', IRE Trans. Electron. Comptit., 1961, 10, pp. 389-400
18. MORAN, J., RIOS, I., and MENESES, J.: 'Siened digit arithmetic on FPGAs', in MOORE, W, and LUK, W. (Eds.): rMore FPGAs' (EE&CS Books, Abington, 1994) p. 250
19. DONACHY, P.: 'Design and implementation of a high-level image processing machine using reconfigurable hardware'. PhD thesis, The Queen's University of Belfast, 1996
20. DUPRAT, J., HERREROS, Y., and MULLER, J.: 'Some results about on-line computation of function'. Proceedings of 9th symposium on Computer arithmetic, Santa Monica, September 1989
21. CROOKES, D., ALOTAIBI, K., BOURIDANE, A., DONACHY, P., and BENKRID, A.: 'An environment for generating FPGA architectures for image algebra based algorithms'. Proceedings of ICIP98, 3, pp. 990-994
22. CLOCKSIN, WE, and MELISH, C.S.: 'Programming in Prolog' (Springer- Verlas, 1994)
23. BENKRID, K., CROOKES, D., SMITH, J., and BENKRID, A.: 'Highlevel programming for real time FPGA-based video processing', to appear Proceedings of ICASSP2000, Istanbul, 2000