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Volumn 2005, Issue , 2005, Pages 19-24

FPGA PLB evaluation using Quantified Boolean Satisfiability

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS; FUNCTION EVALUATION; PROBLEM SOLVING;

EID: 33746867966     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515693     Document Type: Conference Paper
Times cited : (7)

References (14)
  • 3
    • 33746878727 scopus 로고    scopus 로고
    • [Online]
    • Arrow Electronics. [Online], Available: www.arrow.com
    • Arrow Electronics
  • 4
    • 0028259317 scopus 로고
    • An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
    • Jan.
    • J. Cong and Y. Ding, "An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Transactions on Computer-Aided Design, vol. 13, no. 1, pp. 1-13, Jan. 1994.
    • (1994) IEEE Transactions on Computer-aided Design , vol.13 , Issue.1 , pp. 1-13
    • Cong, J.1    Ding, Y.2
  • 5
    • 0027307171 scopus 로고
    • On area/depth trade-off in LUT-based FPGA technology mapping
    • [Online], Available: citeseer.ist.psu.edu/cong94areadepth.html
    • _, "On area/depth trade-off in LUT-based FPGA technology mapping," in Design Automation Conference, 1993, pp. 213-218. [Online], Available: citeseer.ist.psu.edu/cong94areadepth.html
    • (1993) Design Automation Conference , pp. 213-218
  • 8
    • 0033116972 scopus 로고    scopus 로고
    • The hybrid field programmable architecture
    • April-June
    • A.Kaviani and S. Brown, "The hybrid field programmable architecture," IEEE Design and Test, pp. 74-83, April-June 1999.
    • (1999) IEEE Design and Test , pp. 74-83
    • Kaviani, A.1    Brown, S.2
  • 9
    • 0035440923 scopus 로고    scopus 로고
    • Boolean matching for lutta ased logic blocks with applications to architecture evaluation and technology mapping
    • J. Cong and Y.-Y. Hwang, "Boolean matching for lutta ased logic blocks with applications to architecture evaluation and technology mapping," IEEE Transactions on Computer-Aided Design, vol. 20, no. 9, pp. 1077-1090, 2001.
    • (2001) IEEE Transactions on Computer-aided Design , vol.20 , Issue.9 , pp. 1077-1090
    • Cong, J.1    Hwang, Y.-Y.2
  • 10
    • 0026623575 scopus 로고
    • Test pattern generation using Boolean satisfiablity
    • [Online]. Available: citeseer.ist.psu.edu/larrabee92test.html
    • T. Larrabee, "Test Pattern Generation Using Boolean Satisfiablity," IEEE Transactions on Computer-Aided Design, vol. 11, no. 1, pp. 6-22, 1992. [Online]. Available: citeseer.ist.psu.edu/larrabee92test.html
    • (1992) IEEE Transactions on Computer-aided Design , vol.11 , Issue.1 , pp. 6-22
    • Larrabee, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.