-
3
-
-
33746878727
-
-
[Online]
-
Arrow Electronics. [Online], Available: www.arrow.com
-
Arrow Electronics
-
-
-
4
-
-
0028259317
-
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
-
Jan.
-
J. Cong and Y. Ding, "An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Transactions on Computer-Aided Design, vol. 13, no. 1, pp. 1-13, Jan. 1994.
-
(1994)
IEEE Transactions on Computer-aided Design
, vol.13
, Issue.1
, pp. 1-13
-
-
Cong, J.1
Ding, Y.2
-
5
-
-
0027307171
-
On area/depth trade-off in LUT-based FPGA technology mapping
-
[Online], Available: citeseer.ist.psu.edu/cong94areadepth.html
-
_, "On area/depth trade-off in LUT-based FPGA technology mapping," in Design Automation Conference, 1993, pp. 213-218. [Online], Available: citeseer.ist.psu.edu/cong94areadepth.html
-
(1993)
Design Automation Conference
, pp. 213-218
-
-
-
6
-
-
0032681920
-
Cut ranking and pruning: Enabling a general and efficient fpga mapping solution
-
ACM Press
-
J. Cong, C. Wu, and Y. Ding, "Cut ranking and pruning: enabling a general and efficient fpga mapping solution," in Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays. ACM Press, 1999, pp. 29-35.
-
(1999)
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays
, pp. 29-35
-
-
Cong, J.1
Wu, C.2
Ding, Y.3
-
8
-
-
0033116972
-
The hybrid field programmable architecture
-
April-June
-
A.Kaviani and S. Brown, "The hybrid field programmable architecture," IEEE Design and Test, pp. 74-83, April-June 1999.
-
(1999)
IEEE Design and Test
, pp. 74-83
-
-
Kaviani, A.1
Brown, S.2
-
9
-
-
0035440923
-
Boolean matching for lutta ased logic blocks with applications to architecture evaluation and technology mapping
-
J. Cong and Y.-Y. Hwang, "Boolean matching for lutta ased logic blocks with applications to architecture evaluation and technology mapping," IEEE Transactions on Computer-Aided Design, vol. 20, no. 9, pp. 1077-1090, 2001.
-
(2001)
IEEE Transactions on Computer-aided Design
, vol.20
, Issue.9
, pp. 1077-1090
-
-
Cong, J.1
Hwang, Y.-Y.2
-
10
-
-
0026623575
-
Test pattern generation using Boolean satisfiablity
-
[Online]. Available: citeseer.ist.psu.edu/larrabee92test.html
-
T. Larrabee, "Test Pattern Generation Using Boolean Satisfiablity," IEEE Transactions on Computer-Aided Design, vol. 11, no. 1, pp. 6-22, 1992. [Online]. Available: citeseer.ist.psu.edu/larrabee92test.html
-
(1992)
IEEE Transactions on Computer-aided Design
, vol.11
, Issue.1
, pp. 6-22
-
-
Larrabee, T.1
-
11
-
-
33646426964
-
Analysis of search based algorithms for satisfiability of quantified boolean formulas arising from circuit state space diameter problems
-
May
-
D. Tang, Y. Yu, D. P. Ranjan, and S. Malik, "Analysis of search based algorithms for satisfiability of quantified boolean formulas arising from circuit state space diameter problems," in SAT '04: The Seventh International Conference on Theory and Applications of Satisfiability Testing, May 2004, pp. 10-13.
-
(2004)
SAT '04: The Seventh International Conference on Theory and Applications of Satisfiability Testing
, pp. 10-13
-
-
Tang, D.1
Yu, Y.2
Ranjan, D.P.3
Malik, S.4
-
13
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
[Online], Available: citeseer.ist.psu.edu/moskewicz01chaff.html
-
M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," in Proceedings of the 38th Design Automation Conference (DAC'01), 2001. [Online], Available: citeseer.ist.psu.edu/moskewicz01chaff.html
-
(2001)
Proceedings of the 38th Design Automation Conference (DAC'01)
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
|