A networked FPGA-based hardware implementation of a neural network application

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 337-338

  Restrepo, Héctor Fabio ^a   Hoffmann, Ralph ^a   Perez Uribe, Andres ^a   Teuscher, Christof ^a   Sanchez, Eduardo ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTERS; HARDWARE; NEURAL NETWORKS; RECONFIGURABLE HARDWARE;

COMPUTATIONAL ELEMENTS; FIELD PROGRAMMABLES; FLEXIBLE ADAPTABLE-SIZE TOPOLOGIES; FPGA-BASED HARDWARE IMPLEMENTATION; FPGA-BASED IMPLEMENTATION; INTERCONNECTION STRUCTURE; NEURAL NETWORK APPLICATION; RECONFIGURABLE PLAT-FORMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33746207160     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903443     Document Type: Conference Paper

References (4)

1. N. K. Bose and P. Liang. Neural Network Fundamentals with graphs, Algorithms, and Applications. Electrical and Computer Engineering Series. McGraw-Hill, Inc., 1996.
2. A. Pérez-Uribe. Structure-Adaptable Digital Neural Networks. PhD thesis, Swiss Federal Institute of Technology-Lausanne, Lausanne, EPFL, 1999.
3. A. Pérez-Uribe and E. Sanchez. FPGA Implementation of an Adaptable-Size Neural Network. In C. von der Malsburg, W. von Seelen, J. C. Vorbruggen, and B. Sendhoff, editors, Proceedings of the International Conference on Artificial Neural Networks (ICANN96), volume 1112 of Lecture Notes in Computer Science, pages 383-388. Springer-Verlag, Heidelberg, 1996.
4. C. Teuscher, J.-O. Haenni, F. J. Gomez, H. F. Restrepo, and E. Sanchez. A Tool for Teaching and Research on Computer Architecture and Reconfigurable Systems. In Proceedings of the 25th Euromicro Conference, volume 1, pages 343-350. IEEE Computer Society, Milan, Italy, September 8-10 1999.