Systolic architecture for computing the discrete fourier transform on FPGAs

Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005

Volumn 2005, Issue , 2005, Pages 305-306

  Greg Nash, J ^a  

^a Centar ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPRIME NUMBERS; OPTIMAL DESIGNS; SYSTOLIC ARCHITECTURE;

AUTOMATION; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; DISCRETE FOURIER TRANSFORMS; FOURIER TRANSFORMS; SYSTOLIC ARRAYS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746177435     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2005.60     Document Type: Conference Paper

References (4)

1. H. Lim, and E. E. Swartzlander, "Multidimensional systolic arrays for the implementation of discrete Fourier transforms", IEEE Trans. Sig. Proc., Vol.47, No. 5, pp. 13591370, 1999.
2. J. Greg Nash, "Hardware efficient Base-4 systolic architecture for computing the discrete Fourier transform," Proc. IEEE Workshop on Signal Processing Systems, pp.8792, 2002.
3. J. Greg Nash, "Computationally Efficient Systolic Architecture for Computing the Discrete Fourier Transform", to be published IEEE Trans. Sig. Processing.
4. J. Greg Nash, "Automatic generation of systolic array designs for reconfigurable computing", Proc. Int. Conf. Engineering of Reconfigurable Systems and Algorithms (ERSA 02), pp.176-182, CSREA Press, 2002.