Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation

Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005

Volumn 2005, Issue , 2005, Pages 245-254

  Coutinho, José Gabriel F ^a   Jiang, Jun ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL SYNTHESIS TOOLS; HARDWARE COMPILATION; PIPELINE ARCHITECTURES; SCHEDULING ALGORITHMS;

ALGORITHMS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; CONTROL SYSTEM ANALYSIS; RESOURCE ALLOCATION;

COMPUTER HARDWARE;

EID: 33746166042     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2005.44     Document Type: Conference Paper

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