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Volumn 12, Issue 1, 1993, Pages 102-113

Fault Detection and Classification in Linear Integrated Circuits: An Application of Discrimination Analysis and Hypothesis Testing

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EID: 33746099176     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.184847     Document Type: Article
Times cited : (49)

References (23)
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    • A CMOS fault extractor for inductive fault analysis
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    • VLASIC: A catastrophic fault yield simulator for integrated circuits
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.