Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

IEEE Transactions on Computers

Volumn 55, Issue 2, 2006, Pages 113-124

  Phatrapornnant, Teera ^b   Pont, Michael J ^a,b  

^a IEEE   (United Kingdom)

^b UNIVERSITY OF LEICESTER   (United Kingdom)

Author keywords

Low power design; Real time systems and embedded systems; Scheduling

Indexed keywords

DYNAMIC VOLTAGE SCALING; REAL-TIME SYSTEMS AND EMBEDDED SYSTEMS; TIME-TRIGGERED COOPERATIVE (TTC) SCHEDULERS;

COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; JITTER; REAL TIME SYSTEMS; SCHEDULING ALGORITHMS;

EMBEDDED SYSTEMS;

EID: 33745944348     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.29     Document Type: Article

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