An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 84-87

  Lee, Sunghyun ^a   Yoo, Sungjoo ^b   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

^b TIMA LABORATORY   (France)

Author keywords

Dynamic voltage scaling; Finite state machine; Formal model; Low power; Synchronous dataflow; Variable supply voltage

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; FINITE AUTOMATA; OPTIMIZATION; POWER CONTROL; VOLTAGE MEASUREMENT;

DYNAMIC VOLTAGE SCALING METHOD; HIERARCHICAL FINITE STATE MACHINE; SYNCHRONOUS DATAFLOW MODEL; SYSTEM ON CHIP DESIGN;

POWER ELECTRONICS;

EID: 0036949252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/566408.566432     Document Type: Conference Paper

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