Ferroelectric non-volatile logic devices

Integrated Ferroelectrics

Volumn 56, Issue , 2003, Pages 1003-1012

  Fujimori, Y ^a   Nakamura, T ^a   Takasu, H ^a   Kimura, H ^b   Hanyu, T ^b   Kameyama, M ^b  

^a ROHM CO LTD   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; FERROELECTRIC DEVICES; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LSI CIRCUITS; SWITCHING CIRCUITS;

FERROELECTRIC CAPACITORS; LOGIC TECHNOLOGIES; POWER CONSUMPTION;

LOGIC DEVICES;

EID: 33745871444     PISSN: 10584587     EISSN: 16078489     Source Type: Conference Proceeding    
DOI: 10.1080/10584580390259489     Document Type: Article

References (8)

1. 2 2-D Discrete Cosine Transform Core Processor with Variable Threshold Voltage (VT) Scheme," IEEE JSSC 31(11), 1770-1779 (1996).
2. T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gomyo, H. Kawaguchi, and T. Sakurai, "Optimum Device Parameters and Scalability of Variable-Threshold CMOS (VTCMOS)," Abstract of SSDM, 372-373 (2000).
3. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," Journal of Solid-State Circuits 30(8), 847-854 (1995).
4. T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration," IEEE CICC 409-412 (2000).
5. S. Masui, T. Ninomiya, M. Oura, W. Yokozeki, K. Mukaida, and S. Kawashima, "Ferroelectric Memory Based Secure Dynamically Programmable Gate Array," Symp. on VLSI Circuits Dig. of Tech. Papers 200-203, Honolulu (June 2002).
6. Y. Fujimori, T. Nakamura, and H. Takasu, "Electrical Properties of Nonvolatile Latches for New Logic Application," Integrated Ferroelectrics 47, 71-78 (2002).
7. T. Hanyu, H. Kimura, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, "Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation," ISSCC Dig. of Tech. Papers 208-209, San Francisco (Feb. 2002).
8. H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, "Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI," ISSCC Dig. of Tech. Papers 160-161, San Francisco (Feb. 2003).