An effective method for improving IC package die failure during assembly punch processing

Proceedings of the 6th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems - EuroSimE 2005

Volumn 2005, Issue , 2005, Pages 227-233

  Irving, Scott ^a   Liu, Yong ^a   Almagro, Erwin Ian V ^a   Granada Jr , Honorio T ^a  

^a FAIRCHILD SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIE STRESSES; IC PACKAGES; PACKAGE ASSEMBLIES; PUNCH PROCESSING;

ASSEMBLY; ELECTRONIC EQUIPMENT MANUFACTURE; OPTIMIZATION; PUNCH PRESSES; STRESSES;

ELECTRONICS PACKAGING;

EID: 33745726163     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2005.1502806     Document Type: Conference Paper

References (4)

1. Silicon Properties, Engineering Design Research Laboratory, California Institute of Technology.
2. Wu, E., et al., "Influence of Grinding Process on Semiconductor Chip Strength", Proc 2002 Electronic Components and Technology Conference, San Diego, CA, May. 2002, pp. 1617-1621.
3. Joseph Alison King, Materials Handbook for Hybrid Microelectronics, Artech House, Boston, 1998
4. Hughes, T. J. R., The Finite Element Method: Linear Static and Dynamic Finite Element Analysis, Stanford University, 1987