메뉴 건너뛰기




Volumn 2, Issue , 2005, Pages 982-985

Online hardware/software partitioning in networked embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; EVOLUTIONARY ALGORITHMS; ITERATIVE METHODS; ONLINE SYSTEMS;

EID: 33745634653     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120772     Document Type: Conference Paper
Times cited : (8)

References (6)
  • 1
    • 0031628363 scopus 로고    scopus 로고
    • Partitioning sequential circuits on dynamically reconfigurable FPGAs
    • Douglas Chang, Malgorzata Marek-Sadowska, " Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs," International Symposium on FPGAs, 1998.
    • (1998) International Symposium on FPGAs
    • Chang, D.1    Marek-Sadowska, M.2
  • 2
    • 84861448973 scopus 로고    scopus 로고
    • Dynamic load balancing for distributed memory multiprocessors
    • G. Cybertko, " Dynamic Load Balancing for Distributed Memory Multiprocessors," Jozlmel of Parallel and Distributed Systems, pp. 279-301, 1998.
    • (1998) Jozlmel of Parallel and Distributed Systems , pp. 279-301
    • Cybertko, G.1
  • 3
    • 0032308182 scopus 로고    scopus 로고
    • CORDS: Hardware-software Co-synthesis of reconfigurable real-time distributed embedded systems
    • R.Dick, N. Jha, "CORDS: Hardware-Software Co-Synthesis of Reconfigurable Real-Time Distributed Embedded Systems," ICCAD'98, 1998.
    • (1998) ICCAD'98
    • Dick, R.1    Jha, N.2
  • 5
    • 0005231254 scopus 로고    scopus 로고
    • An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA Architectures
    • I. Ouaiss, S. Govindarajan, V. Srirrivasan, M. Kaul, R. Vemuri, li An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures," IPPS/SPDP Workshops, 1998.
    • (1998) IPPS/SPDP Workshops
    • Ouaiss, I.1    Govindarajan, S.2    Srirrivasan, V.3    Kaul, M.4    Vemuri, R.5
  • 6
    • 3042522990 scopus 로고    scopus 로고
    • A self-tuning cache architecture for embedded systems
    • C. Zhang, F. Vahid, R. Lysecky, I' A Self-Tuning Cache Architecture for Embedded Systems," DATE'U4, 2004.
    • (2004) DATE'U4
    • Zhang, C.1    Vahid, F.2    Lysecky, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.