Binary neural networks - A CMOS design approach

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3681 LNAI, Issue , 2005, Pages 1291-1296

  Deshmukh, Amol ^a   Morghade, Jayant ^a   Khera, Akashdeep ^a   Bajaj, Preeti ^a  

^a G H RAISONI COLLEGE OF ENGINEERING   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC GATES; TRANSISTORS;

BINARY CONNECTIONS; DATA CORRUPTION; MULTILAYER NEURAL NETWORK; TWO-PHASE CLOCKING;

NEURAL NETWORKS;

EID: 33745318513     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11552413_184     Document Type: Conference Paper

References (9)

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