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Volumn , Issue , 2005, Pages 340-343

Low complexity parallel chien search architecture for rs decoder

Author keywords

[No Author keywords available]

Indexed keywords

CHIEN SEARCH; GALOIS FIELDS; GF MULTIPLIER; GLOBAL OPTIMIZATION ALGORITHM; GROUP-BASED; LOW COMPLEXITY; MODULO 2; OPTIMIZATION SCHEME; REED SOLOMON;

EID: 33745157734     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464594     Document Type: Conference Paper
Times cited : (12)

References (8)
  • 1
    • 0043270620 scopus 로고    scopus 로고
    • High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder
    • April
    • Hanho Lee, "High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder," IEEE Transactions on Very Large Integration (VLSI) Systems, vol.11, pp.288-294, April 2003.
    • (2003) IEEE Transactions on Very Large Integration (VLSI) Systems , vol.11 , pp. 288-294
    • Lee, H.1
  • 3
    • 84942066984 scopus 로고    scopus 로고
    • An area-efficient Euclidean algorithm block for Reed-Solomon decoder
    • Hanho Lee, "An area-efficient Euclidean algorithm block for Reed-Solomon decoder," in Proc. IEEE Computer Society Annual Symposium on VLSI, 2003, pp. 209 - 210.
    • (2003) Proc. IEEE Computer Society Annual Symposium on VLSI , pp. 209-210
    • Lee, H.1
  • 5
    • 0004400112 scopus 로고    scopus 로고
    • Low complexity modified Mastrovito multipliers over finite fields GF (2m)
    • Orlando, FL, May
    • L.Song and K.K.Parhi, "Low complexity modified Mastrovito multipliers over finite fields GF (2m)," in Proc. of IEEE ISCAS, vol.1, Orlando, FL, May 1999, pp.508-512.
    • (1999) Proc. of IEEE ISCAS , vol.1 , pp. 508-512
    • Song, L.1    Parhi, K.K.2
  • 6
    • 0035392553 scopus 로고    scopus 로고
    • Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials
    • July
    • T.Zhang and K.K.Parhi, "Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials," IEEE Trans .on Computers, vol.50, pp.734-749, July 2001.
    • (2001) IEEE Trans .on Computers , vol.50 , pp. 734-749
    • Zhang, T.1    Parhi, K.K.2
  • 7
    • 0035721166 scopus 로고    scopus 로고
    • Design of A High Performance Reed-Solomon Decoder with Switch Box Control Logic
    • Zhu Hai-kun, Shen Bo and Zhang Qian-ling, "Design of A High Performance Reed-Solomon Decoder with Switch Box Control Logic," in Proc. 4th International Conference on ASIC, 2001, pp.452 - 455.
    • (2001) Proc. 4th International Conference on ASIC , pp. 452-455
    • Zhu, H.-K.1    Bo, S.2    Zhang, Q.-L.3
  • 8
    • 2542485570 scopus 로고    scopus 로고
    • Yanni Chen, Parhi and K.K., Small area parallel Chien search architectures for long BCH codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, pp. 545 - 549, May 2004.
    • Yanni Chen, Parhi and K.K., "Small area parallel Chien search architectures for long BCH codes," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, pp. 545 - 549, May 2004.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.