High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 14-15

  Sanuki, T ^a   Sogo, Y ^c   Oishi, A ^a   Okayama, Y ^a   Hasumi, R ^a   Morimasa, Y ^a   Kinoshita, T ^a   Komoda, T ^a   Tanaka, H ^a   Hiyama, K ^a   Komoguchi, T ^c   Matsumoto, T ^c   Oota, K ^c   Yokoyama, T ^c   Fukasaku, K ^c   Katsumata, R ^b   Kido, M ^b   Tamura, M ^a   Takegawa, Y ^a   Yoshimura, H ^a   Kasai, K ^a   Ohno, K ^c   Saito, M ^c   Aochi, H ^b   Iwai, M ^a   Nagashima, N ^c   Matsuoka, F ^a   Okamoto, Y ^c   Noguchi, T ^a   more..

^a System LSI Division I   (Japan)

^b TOSHIBA CORPORATION   (Japan)

^c SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DATA ACQUISITION; DIELECTRIC MATERIALS; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; TRANSISTORS;

LOGIC TRANSISTOR; SYSTEM ON A CHIP (SOC); ULTRA SHALLOW BURIED STRAP (USBS);

EMBEDDED SYSTEMS;

EID: 33745148650     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469193     Document Type: Conference Paper

References (5)

1. K. Miyashita et al., Symp on VLSI Tech., p. 11 (2001).
2. Y. Matsubara et al., IEDM Tech. Dig., p. 426 (2003).
3. M. Iwai et al., Symp. on VLSI Tech., p. 12 (2004).
4. K. Ota et al., Submitted to Symp. on VLSI Tech., (2005).
5. A. Oishi et al., Symp. on VLSI Tech., p. 166 (2004).