Galois field computation LSI: A reconfigurable chip for high-speed communication

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 208-211

  Endou, Nobuharu ^a   Kasai, Yuji ^b   Iwata, Masaya ^b   Takahashi, Eiichi ^b   Higuchi, Tetsuya ^b  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

^b NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

Adaptive I O; CRC; Galois field; PN generation; Reconfigurable chip; Reed Solomon decoder

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; PERFORMANCE; TELECOMMUNICATION SYSTEMS;

CRC; GALOIS FIELD; PN GENERATION; RECONFIGURABLE CHIP; REED-SOLOMON DECODER;

LSI CIRCUITS;

EID: 33745140556     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469368     Document Type: Conference Paper

References (5)

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