ATM switch design by high-level modeling, formal verification, and high-level synthesis

ACM Transactions on Design Automation of Electronic Systems

Volumn 3, Issue 4, 1998, Pages 554-562

  Rajan, S P ^a   Fujita, M ^a   Yuan, K ^a   Lee, M T C ^b,c  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b Avant Corporation   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

ATM Switch; High Level Design; Synthesis; Verification

Indexed keywords

EID: 33745123126     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/296333.296342     Document Type: Article

References (7)

1. CHANEY, T., FINGERHUT, J. A., FLUCKE, M., AND TURNER, J. 1996. Design of a gigabit ATM switching system. Tech. Rep. WUCS-96-07 (Feb.). Computer Science Dept. Washington Univ. St. Louis.
2. CHEN, B., YAMAZAKI, M., AND FUJITA, M. 1994. Bug identification of a real chip design by symbolic model checking. In Proceedings of the European Conference on Design Automation, the European Test Conference (Paris, France, Feb.). IEEE Computer Society Press, Los Alamitos, CA, pp. 132-136.
3. CURZON, P. 1994. The formal verification of the fairisle ATM switching element. Tech. Rep. 328 and 329 (March). Computer Laboratory, Univ. Cambridge, Cambridge, U.K.
4. LEE, M. T.-C., HSU, Y.-C., CHEN, B., AND FUJITA, M. 1996. Domain-specific high-level modeling and synthesis for ATM switch design using VHDL. In Proceedings of the 33th ACM/IEEE Design Automation Conference. ACM, New York, 585-590.
5. OWRE, S., RAJAN, S., RUSHBY, J., SHANKAR, N., AND SRIVAS, M. 1996. PVS: Combining specification, proof checking, and model checking. In Computer-Aided Verification, CAV '96. (New Brunswick, N.J., July/Aug.). R. Alur and T. A. Henzinger, eds., Lecture Notes in Computer Sciences, vol. 1102. Springer-Verlag, New York, 411-414.
6. RAJAN, S. P., SHANKAR, N., AND SRIVAS, M. 1995. An integration of model-checking with automated proof checking. In Proceedings of the 7th Conference on Computer-Aided Verification (July). P. Wolper, ed., Lecture Notes in Computer Science, vol. 939, Springer-Verlag, New York, 84-97.
7. TAHAR, S., ZHOU, A., SONG, X., CERNY, E., AND KANGEVIN, M. 1996. Formal verification of an ATM switch fabric using mutiway decision graphs. In Proceedings of IEEE 6th Great Lakes Symposium on VLSI (GLS-VLSI'96) (Ames, Iowa, Mar.). IEEE Computer Society Press, Los Alamitos, CA, 106-111.