Advanced wafer thinning technologies to enable multichip packages

2005 IEEE Workshop on Microelectronics and Electron Devices, WMED

Volumn 2005, Issue , 2005, Pages 24-27

  Sandireddy, Sandhya ^a   Jiang, Tom ^a,b  

^a MICRON TECHNOLOGY INC   (United States)

^b IEEE

Author keywords

Backgrind; CMP; DBG

Indexed keywords

COMPUTATION THEORY; MECHANICAL PROPERTIES; POLISHING; WSI CIRCUITS;

BACKGRIND; CMP; DBG;

CHIP SCALE PACKAGES;

EID: 33744461069     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WMED.2005.1431606     Document Type: Conference Paper

References (5)

1. Neil McLellan, Nelson Fan, Shilai Liu, Kim Lau, Jinshen Wu, "Effects of wafer thinning condition on the roughness, Morphology and Fracture strength of silicon die", Transactions of the ASME, Vol. 126, March 2004, pp. 110-114.
2. http://www.disco.co.jp/eg/news/prcsa/20041124_2.html
3. Nathan R Draney, Jun Liu, Tom Jiang, "Experimental Investigation of Bare Silicon Wafer Warp", IEEE Workshop on Microelectronics and Electron Devices, April 2005
4. Joseph Spitzer, "New Advances in thin wafer packaging technology -Remote plasma etching for stress relief process using common backside grinding tape", submitted for Chip Scale Review.
5. www.scz.com