Simultaneous partitioning and frequency assignment for on-chip bus architectures

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 218-223

  Srinivasan, Suresh ^a   Li, Lin ^a   Vijaykrishnan, N ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY ASSIGNMENT; MULTIPROCESSOR APPLICATIONS; ON-CHIP BUS ARCHITECTURES; SIMULTANEOUS PARTITIONING;

COMPUTER ARCHITECTURE; ENERGY UTILIZATION; GENETIC ALGORITHMS; INTERCONNECTION NETWORKS; NATURAL FREQUENCIES; OPTIMIZATION;

MICROPROCESSOR CHIPS;

EID: 33646936613     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.269     Document Type: Conference Paper

References (15)

1. Flynn. AMBA: enabling reusable on-chip designs, IEEE Micro, 1997.
2. CoreConnect Bus Architecture. http://www.chips.ibm.com/products/ coreconnect
3. WishBone Specification. http://www.silicore.net/wishbone.htm.
4. K. Lahiri, G. Lakshminarayana, and A. Raghunathan. LOTTERYBUS: A new communication architecture for high-performance system-on-chip design. In proceedings of Design Automation Conference, June 2001.
5. B.Cordan. An efficient bus architecture for system-on-chip design. In proceedings of Custom Integrated Circuits Conference, 1999.
6. AMBA Specification (rev2.0) and Multi layer AHB specification, Arm: http://www.arm.com, 2001.
7. W.B. Jone, J.S. Wang, H. Lu, I.P.HSU and J.Y.Chen. Segmented Bus design for low-power systems. IEEE transactions on VLSI Systems, March 1999.
8. K. Lahiri, A. Raghunathan and S. Dey. Design space exploration for optimizing on-chip communication architectures. IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2004.
9. C-Ta Hsieh and M. Pedram. Architectural power optimization by bus splitting, Design, Automation and Test in Europe, 2000.
10. th International conference on Supercomputing, 1994.
11. GAUL: Genetic Algorithm Utility Library. http://gaul.sourceforge.net.
12. D. Burger, and T.M. Austin. The simplescalar toolset version 2.0. Technical report 1342, Department of Computer Sciences, The University of Texas at Austin, June 1997.
13. D. Liu and C. Svenoson. Power consumption estimation in CMOS VLSI chips. IEEE Journal on Solid State Circuits, June 1994.
14. N. Manjikian. Multiprocessor enhancement of simplescalar toolset. ACM SIGARCH Computer Architecture News, 2001.
15. S. C. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The splash-2 programs: characterization and methodological considerations. In ISCA-22, pp. 24, 1995.