Fast and accurate Transaction Level Modeling of an extended AMBA2.0 bus architecture

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn 2005, Issue , 2005, Pages 138-139

  Kim, Young Taek ^a   Kim, Taehun ^a   Kim, Youngduk ^a   Shin, Chulho ^a   Chung, Eui Young ^a   Choi, Kyu Myung ^a   Kong, Jeong Taek ^a   Eo, Soo Kwan ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BUSBARS; COMPUTER HARDWARE; COMPUTER SIMULATION; LARGE SCALE SYSTEMS; NETWORK PROTOCOLS; SYSTEMS ANALYSIS;

AMBA2.0 PROTOCOL; RTL; SOC; TRANSACTION LEVEL MODELING (TLM);

COMPUTER ARCHITECTURE;

EID: 33646911075     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.152     Document Type: Conference Paper

References (2)

1. L. Cai, and D. Gajski, "Transaction level modeling : an overview", in IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis,pp. 19-24, 2003.
2. K-M. Lim and Y-D. Kim, "Samsung DVDP Bus & Memory Architecture", Samsung, 21 May. 2002