A comparison of BDDs, BMC, and sequential SAT for model checking

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2003-January, Issue , 2003, Pages 157-162

  Parthasarathy, G ^a   Iyer, M K ^a   Cheng, K T ^a   Wang, L C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Boolean functions; Chromium; Circuits; Data structures; Formal verification; Law; Legal factors; Performance analysis; Robustness; Runtime

Indexed keywords

BOOLEAN FUNCTIONS; CHROMIUM; DATA STRUCTURES; FORMAL VERIFICATION; NETWORKS (CIRCUITS); ROBUSTNESS (CONTROL SYSTEMS);

BOUNDED MODEL CHECKING; LAW; LEGAL FACTORS; PERFORMANCE ANALYSIS; ROBUSTNESS ISSUES; RUNTIMES; SEQUENTIAL CORRELATIONS; WORST-CASE BEHAVIORS;

MODEL CHECKING;

EID: 33746319487     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2003.1252490     Document Type: Conference Paper

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