Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 136-137

  Yamashita, T ^a   Ota, K ^a   Shiga, K ^a   Hayashi, T ^a   Umeda, H ^a   Oda, H ^a   Eimori, T ^a   Inuishi, M ^a   Ohji, Y ^a   Eriguchi, K ^b   Nakanishi, K ^b   Nakaoka, H ^b   Yamada, T ^b   Nakamura, M ^b   Miyanaga, I ^b   Kajiya, A ^b   Kubota, M ^b   Ogura, M ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FIELD EFFECTS; LEAKAGE CURRENTS; MOS DEVICES; MOSFET DEVICES; POLYSILICON; SEMICONDUCTING BORON; SILICA;

ARRAY-TRANSISTORS; INTERLAYER INSULATOR FILMS; LOW STANDBY POWER (LSTP) DEVICES; NITRIDATION TECHNIQUES;

CMOS INTEGRATED CIRCUITS;

EID: 4544283772     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345438     Document Type: Conference Paper

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