A flexible on-chip evolution system implemented on a xilinx virtex-II pro device

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3637 LNCS, Issue , 2005, Pages 66-75

  Glette, Kyrre ^a   Torresen, Jim ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; COST EFFECTIVENESS; EMBEDDED SYSTEMS; EVOLUTIONARY ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; PROGRAM PROCESSORS;

DIGITAL LOGIC; SINGLE-CHIP EVOLUTIONARY SYSTEM; XILINX VIRTEX-II PRO FPGA;

MICROPROCESSOR CHIPS;

EID: 33645989809     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11549703_7     Document Type: Conference Paper

References (16)

1. D. Goldberg. Genetic Algorithms in search, optimization, and machine learning. Addison-Wesley, 1989.
2. I. Kajitani et al. A myoelectric controlled prosthetic hand with an evolvable hardware lsi chip. Technology and Disability, 15(2):129-143, 2003.
3. I. Kajitani, T. Hoshino, N. Kajihara, M. Iwata, and T. Higuchi. An evolvable hardware chip and its application as a multi-function prosthetic hand controller. In Proc. of I6th National Conference on Artificial Intelligence (AAAI-99), pages 182-187, 1999.
4. T. Kalganova. Bidirectional incremental evolution in extrinsic evolvable hardware. In J. Lohn et al., editor, Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, pages 65-74. IEEE Computer Society, Silicon Valley, USA, July 2000.
5. J.F. Miller, D. Job, and V.K. Vassilev. Principles in the evolutionary design of digital circuits - Part 1. Journal of Genetic Programming and Evolvable Machines, 1(1): 8-35, 2000.
6. S. Perkins, P. Porter, and N. Harvey. Self-contained spatially-structured genetic algorithm for signal processing. In J. Miller et al., editors, Evolvable Systems: From Biology to Hardware. Third International Conference, ICES 2000, volume 1801 of Lecture Notes in Computer Science, pages, 165-174. Springer-Verlag, 2000.
7. D. Roggen, Y. Thoma, and E. Sanchez. An evolving and developing cellular electronic circuit. In J. Pollack, M. Bedau, P. Husbands, T. Ikegami, and R. A. Watson, editors, ALife9: Proceedings of the Ninth International Conference on Artificial Life, pages 33-38, Boston, MA, 2004. MIT Press.
8. T. Schmilz et al. Speeding up hardware evolution: A coprocessor for evolutionary algorithms. In P. Hadddow A. Tyrrel and J. Torresen, editors, Evolvable Systems: From Biology to Hardware. Fifth International Conference, ICES'03, volume 2606 of Lecture Notes in Computer Science, pages 274-285. Springer-Verlag, 2003.
9. L. Sekanina and S. Friedl. On routine implementation of virtual evolvable devices using comboo. In Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware, pages 63-70. IEEE, 2004.
10. B. Shackleford et al. A high-performance, pipelined, FPGA-based genetic algorithm machine. Journal of Genetic Programming and Evolvable Machines, 2(1):33-60, 2001.
11. J. Torresen. Evolving multiplier circuits by training set and training vector partitioning. In P. Hadddow A. Tyrrel and J. Torresen, editors, Evolvable Systems: From Biology to Hardware. Fifth International Conference, ICES'03, volume 2606 of Lecture Notes in Computer Science, pages 228-237. Springer-Verlag, 2003.
12. Gunnar Tufte and Pauline C. Haddow. Prototyping a ga pipeline for complete hardware evolution. In 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), pages 18-25, 1999.
13. D. Job V. Vassilev and J. Miller. Towards the automatic design of more efficient digital circuits. In J. Lohn et al., editor, Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, pages 151-160. IEEE Computer Society, Silicon Valley, USA, July 2000.
14. Xilinx Inc. PowerPC 405 Processor Block Reference Guide, August 2004.
15. Xilinx Inc. Embedded System Tools Reference Manual, February 2005.
16. Xilinx Inc. Processor IP Reference Guide, February 2005.