Intrinsic evolution of sorting networks: A novel complete hardware implementation for FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3637 LNCS, Issue , 2005, Pages 46-55

  Kořenek, Jan ^a   Sekanina, Lukáš ^a  

^a BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER NETWORKS; SORTING;

FITNESS FUNCTION; GENETIC UNIT; SORTING NETWORKS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33645972644     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11549703_5     Document Type: Conference Paper

References (16)

1. Devillard, N.: Fast Median Search: An ANSI C Implementation. 1998 http://ndevilla.free.fr/median/median/index.html
2. Hillis, W. D.: Co-evolving parasites improve simulated evolution as an optimization procedure. Physica D 42 (1990) 228-234
3. Imamura, K., Foster, J. A., Krings, A. W.: The Test Vector Problem and Limitations to Evolving Digital Circuits. In: Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, IEEE CS Press, 2000, p. 75-79
4. Juillé, H.: Evolution of Non-Deterministic Incremental Algorithms as a New Approach for Search in State Spaces. In Proc. of 6th Int. Conf. on Genetic Algorithms, Morgan Kaufmann, 1995, p. 351-358
5. Knuth, D. E.: The Art of Computer Programming: Sorting and Searching (2nd ed.), Addison Wesley, 1998
6. Koza, J. R., Bennett III., F. H., Andre, D., Keane, M. A.: Genetic Programming III: Darwinian Invention and Problem Solving. Morgan Kaufmann, 1999
7. Liberouter project, www.liberouter.org
8. Porter, R.: Evolution on FPGAs for Feature Extraction. PhD thesis, Queensland University of Technology, Brisbane, Australia, 2001, p. 229
9. Sekanina, L.: Evolvable components: From Theory to Hardware Implementations, Springer-Verlag, Natural Computing Series, 2003
10. Sekanina, L.: Evolutionary Design Space Exploration for Median Circuits. In: Applications of Evolutionary Computing, Coimbra, Portugalsko, LNCS 3005, Springer Verlag, 2004, p. 240-249
11. Sekanina, L., Friedl, S.: On Routine Implementation of Virtual Evolvable Devices Using COMBO6. In: Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware, Seattle, USA, IEEE Computer Society Press, 2004, p. 63-70
12. Shepherd, R., Foster, J.: Inherent Fault Tolerance in Evolved Sorting Networks. In Proc. of GECCO 2003, LNCS 2723, Springer Verlag, 2003, p. 456-457
13. Sloarch, C., Sharman, K.: The Design and Implementation of Custom Architectures for Evolvable Hardware Using Off-the-Shelf Progarmmable Devices. In: Proc. of the 3rd International Conference on Evolvable Systems: From Biology to Hardware ICES'00, LNCS 1801, Springer-Verlag, Berlin, 2000, p. 197-207
14. Smith, J. I.: Implementing Median Filters in XC4000E FPGAs. Xcell 23, Xilinx, 1996 http://www.xilinx.com/xcell/xl23/xl23_16.pdf
15. Tufte, G., Haddow, P.: Evolving an Adaptive Digital Filter. In: Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware. IEEE Computer Society, 2000, p. 143-150
16. Zhang, Y., Smith, S., Tyrrell, A.: Intrinsic Evolvable Hardware in Digital Filter Design. In: Applications of Evolutionary Computing, Berlin, DE, Springer, LNCS 3005, 2004, p. 389-398