A pipelined low power architectural MPEG-4 video codec chip with deblocking filter for mobile wireless multimedia applications

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn 2, Issue , 2003, Pages 934-937

  Koo, Bontae ^a   Kim, Seongmin ^a   Lee, Seokho ^a   Choi, Minseok ^a   Park, Kihyuk ^a   Eum, Nakwoong ^a   Kim, Jongdae ^a   Cho, Hyunmook ^b  

^a ETRI

^b Kongju National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; IMAGE COMPRESSION; MOTION ESTIMATION; PIPELINES;

CMOS TECHNOLOGY; DE-BLOCKING FILTERING; DEBLOCKING FILTERS; FRAME MEMORY; HIGH QUALITY VIDEO; LOW-POWER CONSUMPTION; MOBILE WIRELESS; MPEG-4 VIDEO CODEC;

MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 33645968216     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277364     Document Type: Conference Paper

References (7)

1. S.M. Park et al "A single-chip video/audio codec tor low bit rate applications " ETRI J. vol 22. no. 1 pp20-29 Mar. 2000
2. T.Hashimoto et al "A 90 mW MPEG video codec LSI with the capability for core profile" ISSCC digest of technical paper. pp140-141, Feb. 2001
3. Sun Deuk Kim et al "A Deblocking Filter with Two Separate Modes in Block-Based Video Coding" IEEE transactions on circuits and systems for video technology, vol 9, No.l Feb. 1999.
4. ISO/IEC, MPEG-4 Video Verification Model version 16.0
5. International Standard ISO/IEC 14496-2 Part2-Visual Annex F.3.1 Deblocking filter
6. Advanced Microcontroller Bus Architecture (AMBA) specification, ARM, 2000
7. Butterfly Microcontroller Handbook, MITEL. Technical Doc. PI 0.6, 1999