A floating-point FPGA-based self-tuning regulator

IEEE Transactions on Industrial Electronics

Volumn 53, Issue 2, 2006, Pages 693-704

  Salcic, Zoran ^a   Cao, Jiaying ^a   Nguang, Sing Kiong ^a  

^a UNIVERSITY OF AUCKLAND   (New Zealand)

Author keywords

Digital signal processor (DSP); Estimation algorithm; Field programmable gate array (FPGA); Floating point arithmetic; Floating point format; Recursive least squares (RLS); Self tuning regulator (STR)

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; FIELD PROGRAMMABLE GATE ARRAYS; MATRIX ALGEBRA; PARAMETER ESTIMATION;

ESTIMATION ALGORITHM; RECURSIVE LEAST SQUARES (RLS) ALGORITHM; SELF-TUNING REGULATOR (STR);

DIGITAL ARITHMETIC;

EID: 33645716480     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2006.871702     Document Type: Article

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