An integrated reset/pulse pile-up rejection circuit for pixel readout ASICs

IEEE Transactions on Nuclear Science

Volumn 53, Issue 1, 2006, Pages 414-417

  Bastia, P ^a   Bertuccio, G ^b   Borghetti, F ^c   Caccia, S ^b   Ferragina, V ^c   Ferrari, F ^a   Maiocchi, D ^d   Malcovati, P ^c   Martin, D ^e   Pullia, A ^d   Ratti, N ^a  

^a Alenia Spazio SpASS   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c UNIVERSITY OF PAVIA   (Italy)

^d UNIVERSITY OF MILAN   (Italy)

^e EUROPEAN SPACE AGENCY   (Netherlands)

Author keywords

Application specific integrated circuit; Front end electronics; Pixel detector; Semiconductor detector; X ray detector

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETECTORS; ELECTRIC POWER UTILIZATION; GAMMA RAYS; IMAGING TECHNIQUES; SPECTROSCOPIC ANALYSIS;

APPLICATION SPECIFIC INTEGRATED CIRCUIT; FRONT END ELECTRONICS; PIXEL DETECTOR; SEMICONDUCTOR DETECTOR; X-RAY DETECTOR;

INTEGRATED CIRCUITS;

EID: 33645682341     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.869852     Document Type: Article

References (5)

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