Reversible-logic design with online testability

IEEE Transactions on Instrumentation and Measurement

Volumn 55, Issue 2, 2006, Pages 406-414

  Vasudevan, Dilip P ^a   Lala, Parag K ^b   Di, Jia ^a   Parkerson, J Patrick ^a  

^a 3202 Bell Engineering Center   (United States)

^b TEXAS A AND M UNIVERSITY TEXARKANA   (United States)

Author keywords

Fredkin gate; Garbage outputs; Online testing; Reversible logic; Toffoli gate; Two pair two rail checker

Indexed keywords

BOOLEAN FUNCTIONS; DESIGN FOR TESTABILITY; DIGITAL CIRCUITS; ENERGY DISSIPATION; ENERGY UTILIZATION; GATES (TRANSISTOR); LOGIC CIRCUITS;

FREDKIN GATE; GARBAGE OUTPUT; ONLINE TESTABILITY; REVERSIBLE-LOGIC DESIGN; TOFFOLI GATE; TWO-PAIR TWO-RAIL CHECKER;

LOGIC DESIGN;

EID: 33645303538     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2006.870319     Document Type: Article

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