Manufacturing test of SoCs

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 317-319

  Kapur, R ^a   Williams, T W ^a  

^a SYNOPSYS INC   (United States)

Author keywords

Built in self test; Circuit testing; Fabrication; Integrated circuit technology; Logic testing; Manufacturing industries; Process design; Pulp manufacturing; Random access memory; Stress

Indexed keywords

FABRICATION; INTEGRATED CIRCUIT TESTING; MANUFACTURE; PROCESS DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM ACCESS STORAGE; STRESSES; SYSTEM-ON-CHIP;

CIRCUIT TESTING; INTEGRATED CIRCUIT TECHNOLOGY; LOGIC TESTING; MANUFACTURING INDUSTRIES; PULP MANUFACTURING; RANDOM ACCESS MEMORY;

BUILT-IN SELF TEST;

EID: 33645241610     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181730     Document Type: Conference Paper

References (4)

1. Semiconductor Industry Association (SIA), "The National Technology Roadmap for Semiconductors", 1999.
2. E.J. Marinissen et al., "Towards a Standard for Embedded Core Test: An Example," Proceedings of the International Test Conference, 1999, pp. 616-627.
3. T.W. Williams and N.C. Brown, "Defect Level as a Function of Fault Coverage," IEEE Transactions on Computers, Vol. C-30, no. 12, 1981, pp. 987-988.
4. Y. Zorian et al., "Testing Embedded Core Based System Chips," Computer, June 1999, pp. 52-60.