Silicon-on-insulator wafers with buried cavities

Journal of the Electrochemical Society

Volumn 153, Issue 4, 2006, Pages

  Suni, T ^a,d   Henttinen, K ^a,d   Dekker, J ^a   Luoto, H ^a,d   Kulawski, M ^a   Makinen J ^b   Mutikainen, R ^c,d  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

^b Okmetic Oyj   (Finland)

^c VTI Technologies Oy   (Finland)

^d ELECTROCHEMICAL SOCIETY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED CAVITIES; DIRECT BONDING; SILICON ON INSULATOR (SOI); WAFERS;

CAVITATION; DIAPHRAGMS; ELECTROCHEMISTRY; ELECTROLYTIC POLISHING; ETCHING; GRINDING (MACHINING); SILICON;

SILICON ON INSULATOR TECHNOLOGY;

EID: 33644798178     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.2167955     Document Type: Article

References (5)

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