Process control issues for retrograde well implants for narrow n+/p+ isolation in CMOS

Proceedings of the International Conference on Ion Implantation Technology

Volumn 22-27-September-2002, Issue , 2002, Pages 17-20

  Rubin, Leonard M ^a   Morris, Wesley ^b   Jasper, Craig ^c  

^a AXCELIS TECHNOLOGIES   (United States)

^b Silicon Engineering   (United States)

^c MOTOROLA INC   (United States)

Author keywords

channeling; ion implant; isolation; shadowing

Indexed keywords

ION IMPLANTATION; IONS; ROBUSTNESS (CONTROL SYSTEMS); SEMICONDUCTING SILICON; THRESHOLD VOLTAGE;

BREAKDOWN PERFORMANCE; CHANNELING; ION IMPLANT; ISOLATION; PROCESS ROBUSTNESS; SHADOWING; SHADOWING EFFECTS; SHALLOW TRENCH ISOLATION;

PROCESS CONTROL;

EID: 33644488418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IIT.2002.1257927     Document Type: Conference Paper

References (2)

1. R. Simonton and L. Rubin, "Channeling Effects in Ion Implantation into Silicon", Chapter 8 in J. Ziegler, ed., Ion Implantation Technology, Ion Implantation Technology Co., 2000, pp. 303-340.
2. C. Sudhama, R. Thoma, M. F. Morris, J. Christiansen, and I.-S. Lim, "Robust Ion-Implantation Process Design Through Statistical Analysis" Proc. of the 3rd Intl. Conf. on Modeling and Simulation of Microsystems, San Diego, March 27-29, 2000.